1. Field of the Invention
This invention relates to bonding-option architectures for integrated circuits (IC), and more particularly, to a bonding-option architecture for use in an IC package which allows selective setting of various logic states to the internal circuit of the IC chip in the IC package.
2. Description of Related Art
In the design of an integrated circuit (IC), a bonding-option architecture is usually provided to the IC so as to allow the user to selectively alter an aspect of the hardware configuration in the IC, which can facilitate the testing and debugging of the IC products. The bonding-option architecture includes a plurality of option pads which can be selectively bonded (called pad bonding) to either a high-voltage point (such as the system power) or a low-voltage point (such as the ground), so as to set various permanent logic states to the internal circuit. The provision of bonding-option architecture in ICs has the benefits of increasing the testability, lowering the costs, expanding the functionality, and adding extra values for the IC products.
Conventional bonding-option architectures include two types: a value-default type and a power/ground proximity type. In the value-default bonding-option architecture, each option pad is factory-preset to a certain logic state, 0 or 1, which can thereafter be altered by wiring the option pad to a proximate power point or ground point. If no wiring is made, the option pad will retain its preset logic state. One drawback to the value-default bonding-option architecture, however, is that, additional power will be consumed after making alternations to the preset logic states on the option pads. This drawback is particularly unacceptable in small-scale computers or compact electronic devices, such as notebook computers or palmtop game machines, where batteries are used as the main power source. In these devices, low-power consumption is a primary concern due to the short period of power utilization from the batteries. Therefore, when the value-default bonding-option architecture is used in ICs that are used in these power-precious machines, it can make these machines less competitive on the market.
On the other hand, the conventional power/ground proximity bonding-option architecture includes a plurality of option pads, each option pad being proximately arranged with a power point and a ground point respectively on the both sides thereof. No default logic states are preset to these option pads. A particular option pad can be set to a logic state of 1 by wiring it to the proximate power point, and to a logic state of 0 by wiring it to the proximate ground point. This type of bonding-option architecture is free from the power-consumptive problem in the value-default bonding-option architecture. However, its proximately arranged power and ground points can cause problems to the overall circuit layout for the IC package, and even an increased noise to the internal circuitry of the IC chip.
In IC designs, it is usually desirable to integrate as many functions as possible in a single IC chip instead of providing these functions in two separate IC chips. However, due to some incompatibility problems in electrical characteristics, it can be sometimes difficult to integrate certain various functions in a single IC chip. When this is the case, it is then desirable to pack the two IC chips in a single MCM (multiple-chip module) IC package so that the two chips can be tested, shipped, and utilized in a convenient and cost-effective manner. In such an MCM IC package, the signals that are transferred from one IC chip to the other can not be observed directly from the IC package. These signals can only be observed from the signal-receiving IC chip. Moreover, the signal-receiving IC chip can not receive externally input signals directly through the package but instead through the other IC chip. This structural and functional complexity makes the testing difficult to carry out, and the test vector can be unsuitable for use on the MCM IC package. The original test vector may have to be rewritten. Therefore, in order to facilitate the testing, one solution is to design the signal-receiving IC chip in an MCM IC package as that shown in FIG. 1A, which, in particular, incorporates a conventional bonding-option architecture.
As shown in FIG. 1A, the IC chip comprises an MCM (multiple-chip module) option pad which includes a value-default bonding-option device 10 and a bonding point 5; an input pad for a first clock signal TXDCLK1, which includes a logic circuit 50 and a bonding point 40; an I/O pad for a second clock signal TXDCLK2, which includes a logic circuit 30 and a bonding point 20; an AND gate 60; and a multiplexer 70. The output of the value-default bonding-option device 10 is denoted by MCMi. The AND gate 60 takes a test signal TEST and the MCMi signal as inputs to thereby produce an output signal DCLKOE whose value is the result of the AND-operation on TEST and MCMi. The output signal DCLKOE from the AND gate 60 serves as the selection signal SEL to the multiplexer 70 in such a manner that when SEL=0, the input at the 0 input end is selected as the multiplexer output, and when SEL=1, the input at the 1 input end is selected. FIG. 1B is a truth table showing the logic relationships among MCMi, TEST, DCLKOE, and SEL. The default logic state to the value-default bonding-option device 10 is 1 (no external wiring is made to the bonding point 5).
FIG. 2A shows one example in which the bonding points 5, 20, 40 in the IC chip of FIG. 1A are externally wired when in use. In the case of FIG. 2A, the bonding point 5 of the value-default bonding-option device 10 is wired to a ground leadframe 80, thereby altering the value of MCMi to 0. The bonding point 20 of the TXDCLK2 I/O pad is non-wired.
FIG. 2B shows the IC chip of FIG. 1A (here denoted by DIE2) being connected to another IC chip (denoted by DIE1). In the case of FIG. 2B, for example, the bonding points 5, 20, 40 in the IC chip DIE2 are such wired that the bonding point 5 of the value-default bonding-option device 10 (MCM option pad) is non-wired; the bonding point 40 of the TXDCLK1 signal input pad is wired to the bonding point 90 of the TXDCLK pad in the signal-sending IC chip DIE1; and the bonding point 20 of the TXDCLK2 signal I/O pad is wired to a corresponding leadframe 98 of the MCM option pad.
It can be learned from the truth table of FIG. 1B that, when TEST=0 (which indicates a normal mode of operation for the signal-receiving IC chip DIE 2), then SEL=0, which causes the multiplexer 70 to select the input signal at its 0 input end as its output (i.e., the output signal TXDCLK from the signal-sending IC chip DIE1, which is transmitted from the logic circuit 95 and the bonding point 90 in the signal-sending IC chip DIE1, subsequently via the bonding point 40 and the logic circuit 50 in the signal-receiving IC chip DIE 2, to the 0 input end of the multiplexer 70). The output of the multiplexer 70 is denoted by TXDCLK1. On the other hand, when TEST=1 (which indicates a test mode of operation for the signal-receiving IC chip DIE 2), then SEL=1, which causes the multiplexer 70 to select the input signal at its 1 input end as its output (i.e., the signal received from an external source via the bonding point 20 of the TXDCLK2 signal I/O pad). In this manner, the TXDCLK1 signal in the signal-receiving IC chip DIE 2 can be obtained directly via the TXDCLK2 I/O pad, instead of via the TXDCLK pad in the signal-sending IC chip DIE1 and the TXDCLK1 input pad in itself. Therefore, with the provision of the value-default bonding-option device 10, the signal-receiving IC chip DIE 2 can be integrated with various functions to meet various application requirements.
Conventionally, a single IC chip is only provided with some fixed functions. However, with the computer systems getting more complex, it is a common practice to provide a single IC chip with various selectable functions that can be set into active operation through a bonding-option means. The provision of a bonding-option architecture in an IC chip for selective activating of various functions in the IC chip is therefore a widely adopted IC design. Further details of the conventional bonding-option architectures with be described in the following.
FIG. 3A is a schematic diagram used to depict the use of a conventional value-default bonding-option device, as designated here by the reference numeral 120. As shown, the value-default bonding-option device 120 includes a passive circuit 110 which is factory-preset to be wired to a POWER point. The passive circuit 110 has a very low resistance that makes it highly conductive. When in conductive state, the passive circuit 110 has virtually no potential drop thereacross. Therefore, the connection of the passive circuit 110 to the preset POWER point allows the setting of a logic state of 1 to the IC internal circuit (not shown) connected to the value-default bonding-option device 120.
FIG. 3B is a schematic diagram used to depict another use of a conventional value-default bonding-option device, as designated here by the reference numeral 140. As shown, the value-default bonding-option device 140 here includes a passive circuit 130 which is factory-preset to be wired to a GROUND point. The passive circuit 130 has a very low resistance that makes it highly conductive. When in conductive state, the passive circuit 130 has virtually no potential drop thereacross. Therefore, the connection of the passive circuit 130 to the preset GROUND point allows the setting of a logic state of 0 to the IC internal circuit (not shown) connected to the value-default bonding-option device 140.
FIG. 4A is a schematic diagram used to depict the utilization of a conventional value-default bonding-option device, as designated here by the reference numeral 220. As shown, the value-default bonding-option device 220 here includes a passive circuit 210 which is factory-preset to be wired to a POWER point. The passive circuit 210 has a very low resistance that makes it highly conductive. When in conductive state, the passive circuit 210 has virtually no potential drop thereacross. Therefore, the connection of the passive circuit 210 to the preset POWER point allows the setting of a logic state of 1 into the IC internal circuit (not shown) connected to the value-default bonding-option device 220. In addition, a GROUND point is arranged in immediate proximity to the POWER point. When a logic setting of 1 is required, no alternation is made to this value-default bonding-option device 220. On the other hand, if the default setting is to be altered from 1 to 0, the technician needs just to wire the POWER point and the proximate GROUND point together to a common ground leadframe.
FIG. 4B is a schematic diagram showing a variation to the value-default bonding-option device 220 of FIG. 4A. As shown, the value-default bonding-option device 220 here differs from the one shown in FIG. 4A only in that the GROUND point is arranged on the other side of the POWER point, but is still in immediate proximity to the POWER point.
FIG. 4C is a schematic diagram used to depict the utilization of a conventional value-default bonding-option device, as designated here by the reference numeral 240. As shown, the value-default bonding-option device 240 here includes a passive circuit 230 which is factory-preset to be wired to a GROUND point. The passive circuit 230 has a very low resistance that makes it highly conductive. When in conductive state, the passive circuit 230 has virtually no potential drop thereacross. Therefore, the connection of the passive circuit 230 to the preset GROUND point allows the setting of a logic state of 0 to the IC internal circuit (not shown) connected to the value-default bonding-option device 240. In addition, a POWER point is arranged in immediate proximity to the GROUND point. When a logic setting of 0 is required, no alternation is made to this value-default bonding-option device 240. On the other hand, if the default setting is to be altered from 0 to 1, the technician needs just to wire the POWER point and the proximate GROUND point together to a common power leadframe.
FIG. 4D is a schematic diagram showing a variation to the value-default bonding-option device 240 of FIG. 4C. As shown, the value-default bonding-option device 240 here differs from the one shown in FIG. 4C only in that the POWER point is arranged instead on the other side of the GROUND point, but is still in immediate proximity to the GROUND point.
One drawback to the foregoing bonding-option architecture is that additional power will be consumed if the default settings are altered in use. This drawback is particularly unacceptable when the value-default bonding-option architecture is used in IC chips that are used in small-scale computers or compact electronic devices, such as notebook computers, where batteries are used as the main power source. The conventional value-default bonding-option architecture, therefore, can make these products less competitive on the market.
FIG. 5 is a schematic diagram showing a conventional power/ground proximity bonding-option architecture. As shown, the power/ground proximity bonding-option architecture includes an option pad 310 which is wired to a BONDING OPTION point. The option pad 310 is similar in structure and function to a typical input pad. In this bonding-option architecture, no default logic states are preset to the option pad 310. The setting of logic states to this bonding-option architecture will be depicted in the following with reference to FIGS. 6A-6B.
As shown in FIG. 6A, the power/ground proximity bonding-option architecture can be arranged in such a manner that a POWER point and a GROUND point are arranged in proximity on both sides of the BONDING OPTION point connected to the option pad 310. When a high-voltage logic state is to be set to the option pad 310, the BONDING OPTION point and the proximate POWER point are wired via respective bonding wires to a common power leadframe (not shown); and whereas when a low-voltage logic state is to be set to the option pad 310, the BONDING OPTION point and the proximate GROUND point are wired via respective bonding wires to a common ground leadframe (not shown).
FIG. 6B is a schematic diagram showing a variation to the value-default bonding-option device of FIG. 6A. As shown, the value-default bonding-option device here differs from the one shown in FIG. 6A only in that the POWER point and the GROUND point are here interchanged in position, but are still arranged in proximity on both sides of the BONDING OPTION point wired to the option pad 310.
The foregoing power/ground proximity bonding-option architecture is more advantageous than the value-default bonding-option architecture in that it will not cause additional power consumption. However, the arrangement of the POWER point and the GROUND point in proximity on both sides of the BONDING OPTION point may not be always achievable in certain designs, in that such an arrangement can cause reliability problems to the IC products, and can affect the overall layout and operation of the IC package. The conventional power/ground proximity bonding-option architecture is therefore still unsatisfactory in use.